Mantaro FPGA IP Cores

Mantaro's FPGA team has developed and tested many useful FPGA cores that are available to drop into an Altera or Xilinx device. These cores can save you valuable time and money during your product development cycle. Mantaro can also customize any available open source core to meet customer requirements. For a product brief on an available Mantaro FPGA IP Core choose from table below:

FPGA IP Core (For a Product Brief click on a link)	Description
AAL1 Structured/Unstructured	Configurable for 8/16/32 T1/E1 full-duplex lines and supports both structured and unstructured modes of operation.
AAL1 Unstructured	Configurable for 8/16/32 T1/E1 full-duplex lines and supports unstructured mode of operation.
ATM TC DS3/E3/STS1	Implements ATM TC UNI functions up to 100 Mbps data-only.
EMAC 10G	10 Gigabit Ethernet MAC (IEEE 802.3ae compliant).
EMAC 40G	40 Gigabit Ethernet MAC (IEEE 802.3ba Draft 1.1) [Under verification].
EMAC 40G/100G	40/100 Gigabit Ethernet MAC (IEEE 802.3ba Draft 1.1) [Under verification].
STS1/STM0 Framer	STS-1 / STM-0 framer designed to process a single stream.
TRIMAC 8-bit	Configurable for 10/100/1000 Mbps MAC with full and half duplex modes of operation (IEEE 802.3 compliant)
TRIMAC 64-bit	Configurable for 10/100/1000 Mbps MAC with full and half duplex modes of operation with 64-bit Rx and Tx data paths(IEEE 802.3 compliant)
Utopia Level 2 Master	Supports 8 and 16 bit modes of operation, up to 31 PHYs, and complies to Utopia Level 2, Version 1.0 specs - Master.
Utopia Level 2 Slave	Supports 8 and 16 bit modes of operation, up to 31 PHYs, and complies to Utopia Level 2, Version 1.0 specs - Slave.