Mantaro FPGA IP Cores and Solutions

Mantaro's FPGA team has developed and tested many useful FPGA cores and solutions that are available to drop into an Altera or Xilinx device. These cores can save you valuable time and money during your product development cycle. Mantaro can customize any available open source core our one of our own cores to meet customer requirements. For a product brief on an available Mantaro FPGA IP Core choose from the table below. Mantaro also offers several development platforms on which these cores have been targeted and tested. Mantaro's cores have true sign once licensing options with NO yearly maintenance fees. Please read product brief for more information.

Ethernet FPGA IP Cores and Solutions (For a Product Brief click on a link)	Description
Watch a Mantaro 100G Ethernet Demo Video!
Ethernet 100G IP Core Solution	100G Ethernet IP Core Solution - 320 bit MAC and PCS @ 312.5 MHz for 100G - IEEE 802.3ba compliant
Ethernet 100G/40G IP Core Solution	40G/100G Ethernet IP Core Solution - Supports Dual-Mode operation with single FPGA image - 320 bit MAC and PCS @ 312.5 MHz for 100G - 320 bit MAC and PCS @ 125 MHz for 40G - IEEE 802.3ba compliant
Ethernet 40G IP Core Solution	40G Ethernet IP Core Solution - 128 bit MAC and PCS @ 312.5 MHz - IEEE 802.3ba compliant
Ethernet MAC 10G/1G	10G/1G Ethernet MAC IP Core - Supports Dual-Mode operation with single FPGA image - 64 bit MAC @ 156.25 MHz for 40G - 64 bit MAC @ 25-125 MHz for 1G - IEEE 802.3ae compliant
Ethernet MAC 10G Low Latency - 32 bit	10G Ethernet MAC IP Core - 32 bit - 32 bit MAC @312.5 MHz for 10G - IEEE 802.3ae compliant - small footprint with lowest latency in industry - Lowest latency MAC; Tx = 41.6ns, Rx = 76.8ns
Ethernet MAC 10G - 64 bit	10G Ethernet MAC core - 64 bit - 64 bit MAC @ 156.25 MHz for 10G - IEEE 802.3ae compliant
Gigabit EMAC	Gigabit Ethernet MAC core - IEEE 802.3 compliant
TRIMAC 8-bit	Configurable for 10/100/1000 Mbps MAC with full and half duplex modes of operation - IEEE 802.3 compliant
TRIMAC 64-bit	Configurable for 10/100/1000 Mbps MAC with full and half duplex modes of operation with 64-bit Rx and Tx data paths - IEEE 802.3 compliant

Other FPGA IP Cores (For a Product Brief click on a link)	Description
AAL1 Struct/Unstruct	Configurable for 8/16/32 T1/E1 full-duplex lines and supports both structured and unstructured modes of operation.
AAL1 Unstructured	Configurable for 8/16/32 T1/E1 full-duplex lines and supports unstructured mode of operation.
ATM TC DS3/E3/STS1	Implements ATM TC UNI functions up to 100 Mbps data-only.
Utopia Level 2 Master	Supports 8 and 16 bit modes of operation, up to 31 PHYs, and complies to Utopia Level 2, Version 1.0 specs - Master.
Utopia Level 2 Slave	Supports 8 and 16 bit modes of operation, up to 31 PHYs, and complies to Utopia Level 2, Version 1.0 specs - Slave.